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US 2016/0111407 A1Published application
Method and system for template assisted wafer bonding using pedestals
AssigneeSkorpios Technologies, Inc.
InventorStephen B. Krasulick
Life of this patent
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Abstract
A multilayer semiconductor has stacks of composite semiconductor materials. Multiple composite devices are bonded on a silicon-on-insulator wafer forming an integrated device.
Claims20
A method of fabricating a multilevel semiconductor structure, the method comprising:
- providing a first substrate including a first plurality of silicon based devices;
- providing a second substrate including a second plurality of devices;
- dicing the second substrate to provide a plurality of dies, each die including one or more of the second plurality of devices;
- providing a third substrate;
- mounting the plurality of dies on predetermined portions of the third substrate;
- aligning the first substrate and the third substrate;
- joining the first substrate and the third substrate to form a composite structure;
- and
- removing at least a portion of the third substrate from the composite structure,
- providing a fourth substrate;
- aligning the fourth substrate with the composite structure;
- and
- joining the fourth substrate and the composite structure to form a semiconductor structure having multiple levels.
10 more elements
A multilevel semiconductor structure comprising:
- a first substrate including a first plurality of devices in a first device layer;
- a first die joined to the first substrate to form a composite structure, wherein:
- the first die is diced from a second substrate;
- and
- the first die is joined to the first substrate using a third substrate;
- a second device layer joined to the first device layer;
- wherein the second device layer is joined to the first device layer using a fourth substrate;
- and
- a second die joined to the second device layer.
6 more elements
Dependencies are inferred from the claim text.