Semiconductor package and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorIlho Kim
Life of this patent
Estimating the term…
Abstract
A method of fabricating a package-on-package (PoP) type of semiconductor package may include providing a lower package with a lower substrate, a lower semiconductor chip, and a lower mold layer and providing an upper package with an upper substrate, an upper semiconductor chip, and an upper mold layer. A through hole is formed to penetrate the upper package, and the upper package and lower package are electrically connected. A thermal interface material is injected into the through hole to form a first heat transmission part between, and in contact with, the upper package and the lower package.
Claims20
A method of fabricating a semiconductor package, the method comprising:
- providing a lower package with a lower substrate, a lower semiconductor chip, and a lower mold layer;
- providing an upper package with an upper substrate, an upper semiconductor chip, and an upper mold layer;
- forming a through hole to penetrate the upper package;
- electrically connecting the upper package to the lower package;
- and
- injecting a thermal interface material into the through hole to form a first heat transmission part between, and in contact with, the upper package and the lower package.
A semiconductor package, comprising:
- a lower package including a lower substrate, a lower semiconductor chip, and a lower mold layer;
- an upper package on the lower package, the upper package including an upper substrate, an upper semiconductor chip, an upper mold layer, and a through hole penetrating the upper substrate and the upper mold layer;
- connection members connecting the lower substrate electrically to the upper substrate;
- and
- a first heat transmission part interposed between the lower package and the upper package.
A method of fabricating a semiconductor package, the method comprising:
- providing a lower package with a lower substrate, a lower semiconductor chip, and a lower mold layer;
- providing an upper package with an upper substrate, an upper semiconductor chip, and an upper mold layer;
- forming a through hole through the upper package;
- positioning the upper package on the lower package with connection members between electrical contacts of the upper package and electrical contacts of the lower package, the connection members being of a height to form a void between a lowermost surface of the upper mold layer of the upper package and an uppermost surface of at least one of the lower semiconductor chip or lower mold layer of the lower package, the void extending in an horizontal direction between the lower package and upper package;
- and
- after positioning the upper package on the lower package, injecting a thermal interface material into the through hole to form a first heat transmission part in the void in contact with the lower package and upper package.
Dependencies are inferred from the claim text.