Planarity-tolerant reworkable interconnect with integrated testing

A structure comprising:

• a substrate comprising a plurality of protrusions on a surface of the substrate;
• and
• a plurality of solder bumps on an opposite surface of the substrate,
• wherein the plurality of protrusions comprises substantially sharp tips that penetrate a solder compound,
• wherein an electrical connection exists between the plurality of protrusions and the plurality of solder bumps.

A structure comprising:

• an electrical interconnection between a first substrate comprising a plurality of protrusions on a first surface of the first substrate;
• a second substrate comprising a plurality of solder bumps on a first surface of the second substrate;
• and
• a plurality of protrusions on a second opposite surface of the second substrate,
• wherein an electrical interconnection exist within the second substrate between the plurality of solder bumps and the plurality of protrusions on the second substrate,
• wherein the plurality of protrusions on the first substrate comprises sharp tips that penetrate the plurality of solder bumps on the second substrate,
• wherein a permanent electrical interconnection is established by physical contact between the plurality of protrusions on the first substrate and the plurality of solder bumps on the second substrate comprising a metallurgical joint.

A method comprising:

• forming a plurality of protrusions on a substrate surface, wherein the substrate comprises a plurality of devices known to be electrically-good;
• and
• forming one or more dies, each of the one or more dies comprises a plurality of protrusions on one side of each of the one or more dies and a plurality of solder bumps on an opposite side of each of the one or more dies, wherein the plurality of protrusions on one side of each of the one or more dies are electrically connected to the plurality of solder bumps within each of the one or more dies,
• wherein, the plurality of protrusions on each of the one or more dies are brought into contact with the plurality of solder bumps on an adjacent die of the one or more dies to form a temporary electrical interconnection comprising a stack of dies,
• wherein the plurality of devices known to be electrically-good are used to test each of the one or more dies to form a chip stack.

A method comprising:

• forming a plurality of protrusions on a first template carrier substrate;
• attaching the first template carrier substrate to a first surface of a second substrate;
• thinning the second substrate to a desired thickness;
• forming a plurality of solder bumps on an opposite second surface of the second substrate;
• using the first template carrier substrate as a handler to attach the plurality of solder bumps to a third substrate comprising a plurality of protrusions to mate with the plurality of solder bumps;
• and
• removing the first template carrier substrate.

A method comprising:

• forming an underfill region between mating surfaces of a first substrate connected to a second substrate, wherein the mating surfaces comprise a plurality of protrusions and a plurality of solder bumps,
• wherein the plurality of protrusions and the plurality of solder bumps are electrically connected to each other by physical contact,
• wherein the underfill region fills a space between the first substrate and the second substrate surrounding the plurality of protrusions and the plurality of solder bumps;
• and
• conducting an electrical test, wherein after a successful test result, the underfill region is cured, forming a permanent electrical interconnection.