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US 2016/0111384 A1Published application
Semiconductor package structure and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHUA-WEI TSENG, SHANG-YUN TU, HSU-HSIEN CHEN, HAO-JUIN LIU, CHEN-SHIEN CHEN, MING HUNG TSENG, CHITA CHUANG
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Abstract
A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate. The conductive pad is coupled with a circuitry of the first semiconductor substrate. The conductive pillar extends along a longitudinal axis and toward the second semiconductor substrate. The conductive pillar includes a sidewall with a rough surface notching toward the longitudinal axis.
Claims21
1:
- A semiconductor package structure, comprising:
- a first semiconductor substrate comprising a conductive pad, wherein the conductive pad is coupled with a circuitry of the first semiconductor substrate;
- and
- a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate, wherein the conductive pillar:
- extends along a longitudinal axis and toward the second semiconductor substrate, and includes a sidewall with a rough surface notching toward the longitudinal axis, and wherein the rough surface comprises a width greater than about 2 μm.
2 more elements
2:
- The semiconductor package structure of claim 1, wherein the width of the rough surface is ranged from about 2 μm to 3.5 μm.
3:
- The semiconductor package structure of claim 1, wherein the sidewall comprises a plurality of protruded portions with a rectangular shape protruding away from the longitudinal axis.
4:
- The semiconductor package structure of claim 1, wherein the sidewall comprises a plurality of protruded portions with a sawtooth shape protruding away from the longitudinal axis.
5:
- The semiconductor package structure of claim 1, wherein the sidewall comprises a plurality of protruded portions with a curved shape protruding away from the longitudinal axis.
6:
- The semiconductor package structure of claim 1, wherein the conductive pad comprises a plurality of recesses, and a bottom surface of the conductive pillar interfaces with the plurality of recesses.
7:
- The semiconductor package structure of claim 1, wherein the conductive pad comprises a rough surface with wavy curves, and a bottom surface of the conductive pillar interfaces with the rough surface.
8:
- The semiconductor package structure of claim 1, further comprising:
- an under bump metallization (UBM) between the conductive pillar and the conductive pad, wherein the UBM comprises a rough surface with a plurality of recesses facing the conductive pillar.
9:
- The semiconductor package structure of claim 1, further comprising:
- a polymeric layer on the first semiconductor substrate, wherein the polymeric layer exposes a portion of the conductive pad, thus allowing a portion of the polymeric layer to remain on the conductive pad;
- and
- an under bump metallization (UBM) between the conductive pillar and the conductive pad, wherein the UBM connects to the conductive pad and interfaces the portion of the polymeric layer on the conductive pad.
1 more element
10:
- The semiconductor package structure of claim 1, wherein the first semiconductor substrate comprises a conductive route underneath the conductive pad and is coupled with the circuitry, and the conductive pad is conformal to an uneven surface resulting from the conductive route.
11:
- The semiconductor package structure of claim 1, further comprising:
- an underfill material between the first and second semiconductor substrates, wherein the underfill material surrounds the sidewall and interfaces the rough surface.
12:
- A semiconductor package structure, comprising:
- a first semiconductor substrate comprising a conductive pad, wherein the conductive pad is coupled with a circuitry of the first semiconductor substrate;
- a passivation layer on the first semiconductor substrate, wherein the passivation layer exposes a portion of the conductive pad;
- a polymeric layer over the first semiconductor substrate, wherein the polymeric layer comprises a layout exposing the portion of the conductive pad and a portion of the passivation layer;
- an interconnector connected to the conductive pad, wherein the interconnector contacts the polymeric layer and the portion of the passivation layer;
- and
- a conductive pillar on the interconnector and disposed over the portion of the passivation layer, wherein the conductive pillar:
- is disposed between the first semiconductor substrate and a second semiconductor substrate, and extends along a longitudinal axis and toward the second semiconductor substrate, and
- includes a sidewall with a rough surface notching toward the longitudinal axis.
6 more elements
13:
- The semiconductor package structure of claim 12, wherein the interconnector comprises an uneven surface interfacing the conductive pillar.
14:
- The semiconductor package structure of claim 12, wherein the exposure of the portion of the passivation layer is underneath the conductive pillar.
15:
- The semiconductor package structure of claim 12, wherein the rough surface includes a roughness (Ra) greater than about 2 μm.
16-20. (canceled)
21:
- A semiconductor package structure, comprising:
- a first semiconductor substrate comprising a conductive pad, wherein the conductive pad is coupled with a circuitry of the first semiconductor substrate;
- and
- a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate, wherein the conductive pillar is extended along a longitudinal axis and toward the second semiconductor substrate;
- and
- a dielectric layer between the first semiconductor substrate and the second semiconductor substrate, wherein the dielectric layer surrounds and interfaces a sidewall of the conductive pillar, and the sidewall of the conductive pillar and a sidewall of the dielectric layer are engaged to each other.
3 more elements
22:
- The semiconductor package structure of claim 21, wherein the sidewall of the conductive pillar has a plurality of first protruded portions, the sidewall of the dielectric layer has a plurality of second protruded portions, and the first protruded portions and the second protruded portions are engaged to each other.
23:
- The semiconductor package structure of claim 22, wherein the first protruded portion and the second protruded portion overlap each other in the longitudinal axis, thereby forming an overlapping area, and a width of the overlapping area is greater than about 2 μm.
24:
- The semiconductor package structure of claim 22, wherein the sidewall of the conductive pillar has a plurality of first notches disposed alternately with the first protruded portions, the sidewall of the dielectric layer has a plurality of second notches disposed alternately with the second protruded portions.
25:
- The semiconductor package structure of claim 24, wherein a length of the first protruded portion parallel to the longitudinal axis is greater than a length of the first notch parallel to the longitudinal axis.