Semiconductor structures and fabrication method thereof

#This application claims the priority of Chinese patent application No. 201410549387.6, filed on Oct. 16, 2014, the entirety of which is incorporated herein by reference.

#The present invention generally relates to the field of semiconductor manufacturing technology and, more particularly, relates to a semiconductor structure and the fabricating process thereof.

#With the progress of very-large-scale integration (VLSI) technology, the feature size of the semiconductor structure is continuously shrinking, the chip area is persistently getting bigger, and RC (R means resistance while C refers to the capacitance) delay problem of semiconductor structure becomes more and more significant. In particular, the growing influence of the line capacitance between the metal wiring results in a significant decline in device performance and it has become a key constraint to further development of the semiconductor industry.

#FIG. 1-3 illustrate schematic cross-section views of semiconductor structures corresponding to certain stages of a fabrication process in current practice;

#FIGS. 4-10 illustrate schematic cross-section views of semiconductor structures corresponding to certain stages of an exemplary fabrication process consistent with the disclosed embodiments; and

#FIG. 11 illustrates an exemplary fabrication process of a semiconductor structure consistent with the disclosed embodiments.

#Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

#As described above in the background section, a new semiconductor structure and a corresponding fabricating method are desired to meet with the development trend of miniaturization and microminiaturization of semiconductor technology. In current practice, referring to FIG. 1-3, the process to form a semiconductor structure includes the following steps.

#As shown in FIG. 1, a substrate 100 is provided and a number of underlying metal layers 101 have been formed in the substrate 100. A dielectric layer 102 is then formed on the surface of the substrate 100 and a mask layer 103 is formed on the surface of the dielectric layer 102. Further, a number of openings 104 are formed in the mask layer 103 and the surface of the dielectric layer 102 is exposed on the bottom of the openings 104.