Electrical Connections for Chip Scale Packaging
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Wei Chen, Shih-Wei Liang
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Abstract
Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.
Claims20
A device comprising:
- a substrate having a center region and having peripheral regions;
- a conductive line on the substrate;
- and
- a passivation layer formed on the conductive line, the passivation layer having a plurality of apertures exposing respective regions of the conductive line, a longest one of the plurality of apertures having a major axis extending in a direction along a major plane of the substrate, the direction being substantially perpendicular to a stress vector, the stress vector caused by a difference in a respective coefficients of thermal expansion between at least two materials on the substrate.
A device comprising:
- a plurality of device layers including a post-passivation layer, at least two of the device layers having a difference in respective coefficients of thermal expansion;
- and
- a plurality of elongated apertures in the post-passivation layer, a longest one of the plurality of elongated apertures having a major axis extending substantially perpendicular to a first direction, the first direction corresponding to a direction of stress caused by the difference in respective coefficients of thermal expansion.
A method of manufacturing a semiconductor device comprising:
- providing a plurality of device layers including a post-passivation layer, at least two of the device layers having a first direction of coefficient of thermal expansion mismatch;
- patterning the post-passivation layer to include a first elongated aperture having a first length extending in a second direction substantially perpendicular to the first direction, and a plurality of second apertures, each second aperture having a length shorter than the first length and extending in the second direction;
- lining the first elongated aperture and the plurality of second apertures with a undercontact metallization layer;
- and
- filling the first elongated aperture and the plurality of second apertures with a conductor.
Dependencies are inferred from the claim text.