Semiconductor device
AssigneePS4 Luxco S.a.r.I.
InventorYoshihiro Takaishi
Life of this patent
Estimating the term…
Abstract
One semiconductor device includes one parallel transistor for connecting in parallel multiple vertical transistors disposed in an active region on a semiconductor substrate. The parallel transistor includes: semiconductor pillars that project out in a direction perpendicular to a main surface of the semiconductor substrate; a lower diffusion layer that is disposed below the semiconductor pillars; upper diffusion layers that are each disposed on an upper section of the semiconductor pillars; and gate electrodes disposed, with a gate insulator film therebetween, on the entire side surfaces of the semiconductor pillars. The upper diffusion layers are connected to one upper contact plug that is disposed over the upper diffusion layers.
Claims15
A semiconductor device comprising one parallel transistor in which a plurality of vertical transistors disposed in an active region on a semiconductor substrate are connected in parallel, wherein the parallel transistor comprises:
- a plurality of semiconductor pillars protruding out in a direction perpendicular to a main surface of the semiconductor substrate;
- a lower diffusion layer disposed below the plurality of semiconductor pillars;
- a plurality of upper diffusion layers, disposed respectively at the top of the plurality of semiconductor pillars;
- and
- a gate electrode disposed over the side surfaces, in their entirety, of the plurality of semiconductor pillars, with the interposition of a gate insulating film;
- and wherein the plurality of upper diffusion layers are connected to one upper contact plug disposed on the plurality of upper diffusion layers.
A semiconductor device comprising:
- an element isolation region disposed in a main surface of a semiconductor substrate;
- a first active region and a second active region which are enclosed by the element isolation region and are adjacent to one another in a first direction;
- and
- an intermediate element isolation region sandwiched between the first active region and the second active region;
- wherein the first active region comprises:
- a first semiconductor pillar adjacent to the intermediate element isolation region;
- a first upper diffusion layer located at the top of the first semiconductor pillar;
- a second semiconductor pillar adjacent, in the first direction, to the first semiconductor pillar;
- a second upper diffusion layer located at the top of the second semiconductor pillar;
- and
- a continuous first gate electrode enclosing the peripheries of the first semiconductor pillar and the second semiconductor pillar;
- the second active region comprises:
- a third semiconductor pillar adjacent to the intermediate element isolation region;
- a third upper diffusion layer located at the top of the third semiconductor pillar;
- a fourth semiconductor pillar adjacent, in the first direction, to the third semiconductor pillar;
- a fourth upper diffusion layer located at the top of the fourth semiconductor pillar;
- and
- a continuous second gate electrode enclosing the peripheries of the third semiconductor pillar and the fourth semiconductor pillar;
- and
- the intermediate element isolation region comprises:
- a dummy pillar extending in the first direction, spanning between the first active region and the second active region;
- and
- a power-feed gate electrode enclosing the periphery of the dummy pillar;
- the first gate electrode and the second gate electrode are each connected to the power-feed gate electrode;
- the first upper diffusion layer and the second upper diffusion layer are connected to one first upper contact plug;
- and
- the third upper diffusion layer and the fourth upper diffusion layer are connected to one second upper contact plug.
A semiconductor device comprising:
- an element isolation region disposed in a main surface of a semiconductor substrate;
- and
- a first active region and a second active region which are enclosed by the element isolation region and are adjacent to one another in a first direction, with the interposition of an intermediate element isolation region;
- wherein the first active region comprises:
- first and second semiconductor pillars which are adjacent to the intermediate element isolation region and are adjacent to one another in a second direction orthogonal to the first direction;
- first and second upper diffusion layers located respectively at the top of the first and second semiconductor pillars;
- and
- a continuous first gate electrode enclosing the peripheries of the first semiconductor pillar and the second semiconductor pillar;
- the second active region comprises:
- third and fourth semiconductor pillars which are adjacent to the intermediate element isolation region and are adjacent to one another in the second direction orthogonal to the first direction;
- third and fourth upper diffusion layers located respectively at the top of the third and fourth semiconductor pillars;
- and
- a continuous second gate electrode enclosing the peripheries of the third semiconductor pillar and the fourth semiconductor pillar;
- and
- the intermediate element isolation region comprises:
- a dummy pillar extending in the first direction, spanning between the first active region and the second active region;
- and
- a power-feed gate electrode enclosing the periphery of the dummy pillar;
- the first gate electrode and the second gate electrode are each connected to the power-feed gate electrode;
- and
- the first upper diffusion layer to the fourth upper diffusion layer are connected to one upper contact plug.
Dependencies are inferred from the claim text.