Compact Multi-Die Power Semiconductor Package

A power semiconductor package comprising:

• a sync transistor having a drain on a top surface of said sync transistor, and a source and a gate on a bottom surface of said sync transistor;
• said source of said sync transistor configured for attachment to a first partially etched leadframe segment and said gate of said sync transistor configured for attachment to a second partially etched leadframe segment;
• a control transistor having a source and a gate on a top surface of said control transistor, and a drain on a bottom surface of said control transistor;
• said drain of said control transistor configured for attachment to a third partially etched leadframe segment;
• a conductive clip extending to said substrate and situated over said drain of said sync transistor and said source of said control transistor, said conductive clip coupling said drain of said sync transistor and said source of said control transistor to said substrate without using a leadframe;
• a second conductive clip situated over and coupled to said gate of said control transistor;
• an integrated circuit configured for attachment to a fourth partially etched leadframe segment, said integrated circuit coupled to said gate of said control transistor and to said gate of said sync transistor.