Compact Single-Die Power Semiconductor Package
AssigneeInternational Rectifier Corporation
InventorEung San Cho
Life of this patent
Estimating the term…
Abstract
Disclosed is a power semiconductor package including a power transistor having a first power electrode and a gate electrode on its top surface and a second power electrode on its bottom surface. The second power electrode is configured for attachment to a partially etched leadframe segment, where the partially etched leadframe segment is attached to a substrate. A conductive clip is situated over the first power electrode and extends to the substrate in order to couple the first power electrode to the substrate without using a leadframe.
Claims20
A power semiconductor package comprising:
- a power transistor having a first power electrode and a gate electrode on a top surface of said power transistor, and a second power electrode on a bottom surface of said power transistor;
- said second power electrode being configured for attachment to a partially etched leadframe segment, said partially etched leadframe segment having a uniform thickness across an entire length thereof and being configured for attachment to a substrate;
- a first conductive clip situated over said first power electrode and extending to said substrate, said first conductive clip coupling said first power electrode to said substrate without using a leadframe.
A power semiconductor package comprising:
- a power FET having a source electrode and a gate electrode on a top surface of said power FET, and a drain electrode on a bottom surface of said power FET;
- said drain electrode being configured for attachment to a partially etched leadframe segment, said partially etched leadframe segment having a substantially uniform thickness across an entire length thereof and being configured for attachment to a circuit board;
- a first conductive clip situated over said source electrode and extending to said circuit board, said first conductive clip coupling said source electrode to said circuit board without using a leadframe, thereby reducing a size of said power semiconductor package.
A power semiconductor package comprising:
- a power FET having a drain electrode and a gate electrode on a top surface of said power FET, and a source electrode on a bottom surface of said power FET;
- said source electrode being configured for attachment to a partially etched leadframe segment, said partially etched leadframe segment having a uniform thickness across an entire length thereof and being configured for attachment to a circuit board;
- a first conductive clip situated over said drain electrode and extending to said circuit board, said first conductive clip coupling said drain electrode to said circuit board without using a leadframe, thereby reducing a size of said power semiconductor package.
Dependencies are inferred from the claim text.