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US 2016/0111347 A1Published application
Semiconductor package and method of fabricating the same
OwnerJongkook Kim, Su-min Park +5inventors
InventorsJongkook Kim, Su-min Park, Soojeoung Park, Bona Baek, Hohyeuk Im, Byoungwook Jang, Yoonha Jung
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Abstract
Provided are a semiconductor package and a method of fabricating the same. The package substrate includes a hole, which may be used to form a mold layer without any void. The mold layer may be partially removed to expose a lower conductive pattern. Accordingly, it is possible to improve routability of solder balls.
Claims1
A semiconductor package, comprising:
- a package substrate including at least one hole;
- at least one lower conductive pattern on a bottom surface of the package substrate;
- at least one semiconductor chip mounted on the package substrate in a flip-chip bonding manner;
- and
- a mold layer on the package substrate, the mold layer including,
- an upper mold portion covering the at least one semiconductor chip and a top surface of the package substrate, and
- a lower mold portion connected to the upper mold portion through the at least one hole to cover at least a portion of the bottom surface of the package substrate and expose at least a portion of the lower conductive pattern, and the lower mold portion including a mold bottom surface defining a lower mold hole exposing the at least one portion of the lower conductive pattern.
4 more elements
Dependencies are inferred from the claim text.