Semiconductor device including gate channel having adjusted threshold voltage

A method of controlling a voltage threshold of a semiconductor device, the method comprising:

• forming an nFET region on a semiconductor substrate, and at least one first semiconductor fin having a fin thickness on the nFET region, the at least one first semiconductor fin having an nFET channel region interposed between a pair of nFET source/drain regions;
• forming a plurality of pFET regions on the semiconductor substrate, and forming a second semiconductor fin on each pFET region, the second semiconductor fin having a pFET channel region interposed between a pair of pFET source/drain regions;
• and
• forming a plurality of epitaxial liners having different doping concentrations with respect to one another, each epitaxial liner formed in a respective pFET region such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel region of a respective second semiconductor fin, the epitaxial liners including an etched pFET channel portion,
• wherein a combination of the etched pFET channel portion and the epitaxial liners defines a combined thickness that is equal to the fin thickness of the at least one first semiconductor fin.