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US 2016/0111330 A1Published application
Method for producing interconnections for 3d integrated circuit
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsClaire FENOUILLET-BERANGER, Philippe CORONEL
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Abstract
Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer formed between two superimposed levels of transistors, then the removal of the sacrificial elements through the porous layer and their replacement by a conductor material before or after having produced a higher level transistor.
Claims12
A method for producing one or more connection elements for integrated circuit including the steps consisting in:
- producing one or more sacrificial elements passing through at least one porous layer, the porous layer surmounting a first transistor produced at least partially in a first semi-conductor layer, the production of the sacrificial elements including the formation of one or more first openings passing through the porous layer then the filling of the first openings by means of a sacrificial material,
- forming a support on the porous layer, this support including a second semi-conductor layer, at least one second transistor being produced at least partially in the second semi-conductor layer,
- the method further including, after producing the sacrificial elements, the steps consisting in:
- removing the first openings, the sacrificial element(s) using an etching agent of the sacrificial material, the etching agent being capable of being introduced through the porous layer,
- filling the first openings by means of a conductor material so as to form connection elements using one or more second openings made in the support and emerging respectively on at least one of the first openings.
2 more elements
Dependencies are inferred from the claim text.