Methods of Fabricating Tape Film Packages
AssigneeSamsung Electronics Co., Ltd.
InventorsJeong-Kyu HA, Youngshin KWON, KwanJai LEE, Jae-Min JUNG, KyongSoon CHO, Sang-Uk HAN
Life of this patent
Estimating the term…
Abstract
A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.
Claims10
A method of fabricating a tape film package comprising:
- providing an insulating pattern having a user region and a test region defined by a cutting line;
- forming a via hole in the insulating pattern of the user region;
- forming a via contact in the via hole in the insulating pattern;
- forming first and second interconnection patterns connected to the via contact on an upper surface and a lower surface of the insulating pattern respectively, wherein the first interconnection pattern extends from the user region to the test region, the second interconnection pattern is shorter than the first interconnection pattern in the user region and spaced apart from the cutting line of the insulating pattern;
- and
- forming a solder resist on the second interconnection pattern,
- wherein the second interconnection pattern includes an interconnection region between the insulating pattern and the solder resist, and a pad region exposed by the solder resist from the interconnection region to an end of the second interconnection pattern adjacent the cutting line.
A method of fabricating a tape film package comprising:
- providing an insulating pattern having a user region and a test region defined by a cutting line;
- forming a via contact in the insulating pattern of the user region, the via contact exposed on an upper surface and a lower surface of the insulating pattern;
- forming first and second interconnection patterns connected to the via contact on the upper surface and the lower surface of the insulating pattern respectively, wherein the first interconnection pattern extending from the user region to the test region, and the second interconnection pattern is shorter than the first interconnection pattern in the user region and spaced apart from the cutting line of the insulating pattern;
- and
- forming a solder resist on the second interconnection pattern,
- wherein the second interconnection pattern includes an interconnection region between the insulating pattern and the solder resist, and a pad region exposed by the solder resist from the interconnection region to an end of the second interconnection pattern adjacent the cutting line;
- and
- wherein the solder resist is formed between a sidewall of the second interconnection patterns and the cutting surface.
Dependencies are inferred from the claim text.