Manufacturing method of wafer level chip scale package structure

A manufacturing method of a wafer level chip scale package structure comprising:

• providing a wafer having a plurality of semiconductor devices, wherein a first semiconductor device of the semiconductor devices has an active surface and a back surface, the active surface has an active region and an outer region, a first electrode and a second electrode are arranged in the active region, and the outer region is divided into a cutting portion and a channel portion;
• forming an patterned protecting layer on the active surface, wherein the patterned protecting layer has a plurality of openings to respectively expose the first electrode, the second electrode, and the channel portion;
• performing a thinning process from the back surface;
• forming a back electrode layer on the back surface;
• performing an etching process to form a trench exposing the back electrode layer at the channel portion;
• forming a conductive structure through the trench to connect the back electrode layer;
• and
• performing a cutting process along the cutting portion.