Charge trapping split gate embedded flash memory and associated methods

A method of making a memory cell and a logic gate on a semiconductor substrate, the method comprising:

• forming a dielectric layer in a first region and a second region of the semiconductor substrate;
• disposing a gate conductor layer over the dielectric layer;
• forming a select gate mask in the first region;
• removing one or more regions adjacent to the select gate mask in the first region;
• disposing a charge dielectric layer over the first and second regions;
• forming a gate structure for the memory cell in the first region, wherein forming the gate structure comprises:
• removing the charge dielectric layer over the, second region;
• and
• patterning the charge dielectric layer in the first region;
• and
• forming a logic gate in the second region after removal of the charge dielectric layer over the second region.