Memory device and memory system including the same
AssigneeSK hynix Inc.
InventorsJong-Yeol YANG, Jung-Taek YOU, Ga-Ram PARK
Life of this patent
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Abstract
A memory device may include an address latch circuit that latches an address received from an exterior of the memory device, a repair signal generation circuit that generates a soft repair signal, a selection information generation circuit that generates first selection information by using first bits of a latched address latched by the address latch circuit, first to Nth register circuits that store second bits of the latched address as repair data by being selected by the first selection information when the soft repair signal is activated, and first to Nth memory blocks that perform repair operations using the repair data stored in the respective first to Nth register circuits.
Claims15
A memory device comprising:
- an address latch circuit configured to latch an address received from an exterior of the memory device;
- a repair signal generation circuit configured to generate a soft repair signal;
- a selection information generation circuit configured to generate first selection information by using first bits of a latched address latched by the address latch circuit;
- first to Nth register circuits configured to store second bits of the latched address as repair data, the first to Nth register circuits being selected by the first selection information when the soft repair signal is activated;
- a selection information selection unit configured to transfer the first selection information to the first to Nth register circuits when the soft repair signal is activated, and transfer second selection information to the first to Nth register circuits in a boot-up operation;
- and
- first to Nth memory blocks configured to perform repair operations using the repair data stored in the respective first to Nth register circuits,
- wherein the N is an integer greater than 1.
A method for operating a memory device including first to Nth memory blocks and first to Nth register circuits that store repair data of the respective first to Nth memory blocks, comprising:
- entering a soft repair mode;
- receiving an address representing a defective memory cell of the memory blocks together with an active command, and temporarily storing the address;
- deciding whether to perform a soft repair operation by checking states of one or more data pads in response to a write command;
- storing second bits of a temporarily stored address in a circuit of the first to Nth register circuits, which is selected using first bits of the temporarily stored address, as repair data when the soft repair operation is decided to be performed, and providing a second selection information for selecting the circuit of the first to Nth register circuits in a boot-up operation, and wherein the N is an integer greater than 1.
(canceled)
A method for operating a memory system including a memory device including first to Nth memory blocks and first to Nth register circuits for storing repair data of the respective first to Nth memory blocks and a memory controller that controls the memory device, comprising:
- controlling the memory device to enter a soft repair mode, by the memory controller;
- applying an address representing a defective memory cell of the memory blocks together with an active command from the memory controller to the memory device;
- temporarily storing the address in the memory device;
- applying a write command from the memory controller to the memory device;
- deciding whether to perform a soft repair operation by checking logic states of one or more data pads by the memory device in response to the applying of the write command;
- and
- storing second bits of a temporarily stored address in a circuit of the first to Nth register circuits, which is selected using first bits of the temporarily stored address, as repair data when the soft repair operation is decided to be performed, and providing a second selection information for selecting the circuit of the first to Nth register circuits in a boot-up operation, and wherein the N is an integer greater than 1.
Dependencies are inferred from the claim text.