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US 2016/0111170 A1Published application
Method and apparatus for testing memory
AssigneeNXP USA, Inc.
InventorsYunwu Zhao, Hao Wang
Life of this patent
Estimating the term…
Abstract
In an integrated circuit, a first scan chain of flip-flops is loaded with data for testing data retention of the flip-flops and a memory is loaded with data for performing a retention test by a memory built-in self-test (MBIST) wrapper circuit. A portion of the system is placed in a low-power state for a predetermined period of time before data is read from the memory and retention of data by the memory while in the low-power state is determined.
Claims18
A method of testing operation of a memory of an integrated circuit, comprising:
- loading a first scan chain of flip-flops with first data for testing data retention of the flip-flops;
- loading the memory with second data for performing a retention test by a memory built-in self-test (MBIST) wrapper circuit;
- placing at least a portion of the integrated circuit and the memory in a low-power state for a predetermined period of time;
- reading the second data from the memory;
- and
- determining retention of the second data by the memory in the low-power state based on the read data.
3 more elements
A system, comprising:
- a memory for storing data;
- a memory built-in self-test (MBIST) wrapper circuit coupled to the memory for testing operation of the memory, wherein the MBIST wrapper circuit stores retention data in the memory;
- a scan chain of flip-flops having an input and an output, wherein the scan chain receives scan data via the input and stores the scan data therein;
- combinational logic;
- and
- a power management control (PMC) unit for controlling an operating voltage of at least the combinational logic,
- wherein the PMC unit initiates a low-power mode in which an operating voltage of at least the combinational logic is reduced for a predetermined period of time, and
- the MBIST wrapper circuit reads the retention data from the memory and determines retention of data by the memory based on the read data.
5 more elements
An integrated circuit, comprising:
- a memory for storing data;
- a memory test unit coupled to the memory for testing an operation of the memory;
- a plurality of flip-flops connected together into a serial scan chain;
- a power management control unit (PMCU) for controlling an operating voltage of a portion of the integrated circuit;
- and
- a test control unit (TCU) for loading scan data into the scan chain of flip-flops and causing the memory test unit to load retention data into the memory for a memory retention test,
- wherein the PMCU reduces the operating voltage of a logic portion of the system and the memory for a predetermined period of time, and
- the TCU determines the retention of the data in the memory after the reduction in the operating voltage.
5 more elements
Dependencies are inferred from the claim text.