Memory test apparatus

A memory test apparatus comprising:

• a test board unit comprising a plurality of test boards configured to load for testing a plurality of memory systems;
• a power unit comprising a plurality of power supply units respectively corresponding to the plurality of test boards and providing the plurality of test boards with powers required for testing;
• and
• a power supply control unit configured to set timings during which the plurality of power supply units provide the powers required for testing and adjusts time intervals between the respective timings.

A test system comprising:

• a plurality of test boards each including a plurality of memory devices;
• a plurality of power supplies, each power supply powering a respective test board;
• and
• a power supply control unit configured to separately gate each power supply with a respective timing to optimize a performance of each test board.