Apparatuses and methods for reducing read disturb

An apparatus, comprising:

• a plurality of memory subblocks including a plurality of select gate source switches;
• an access line associated with each of the plurality of subblocks;
• and
• a control unit coupled to each of a plurality of memory subblocks, the control unit configured to enable select gate source switches of the plurality of memory subblocks and to provide a control signal to each of the plurality of memory subblocks at a first voltage using the access line, the control unit further configured to selectively disable each of the plurality of select gate source switches of the plurality of memory subblocks responsive, at least in part, to providing the control signal at the first voltage and to provide the control signal to each of the plurality of memory subblocks at a second voltage using the access line responsive, at least in part, to selectively disabling each of the plurality of select gate source switches of the plurality of memory subblocks.

A method, comprising:

• enabling a select gate source switch of a first memory subblock and a second gate source switch of a second memory subblock;
• providing a control signal on an access line associated with the first memory subblock and the second memory subblock;
• increasing a voltage of the control signal to a first voltage;
• disabling the select gate source switch of the first memory subblock;
• and
• increasing the voltage of the control signal from the first voltage to a second voltage.

A method, comprising:

• providing a control signal on each of a plurality of access lines during a read operation;
• increasing the voltage of the control signal while each of a plurality of select gate drain switches and each of a plurality of select gate source switches are enabled;
• selectively disabling each of the plurality of select gate drain switches and each of the plurality of select gate source switches;
• and
• increasing the voltage of the control signal.

A method, comprising:

• providing an active control signal on first and second select gate source lines, the first select gate source line associated with a first plurality of subblocks and the second select gate source line associated with a second plurality of subblocks;
• providing a control signal at a first voltage to each of the first and second pluralities of subblocks;
• providing an inactive control signal on the first select gate source line;
• and
• providing a control signal at a second voltage to each of the first and second pluralities of subblocks, the second voltage greater than the first voltage.