US 2016/0111164 A1Published application

Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory

AssigneeSanDisk Technologies LLC

InventorsHong-Yan Chen, Yingda Dong, Ching-Huang Lu

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Abstract

Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.

Claims31

Dependent claims

A method for operating a memory device, comprising:

performing a programming operation involving a set of memory cells, each memory cell of the set of memory cells comprises a charge-trapping layer, a control gate, a drain, a source and a channel, and the performing the programming operation comprises configuring the memory cells to provide a positive gate-to-channel voltage for the memory cells, the configuring the memory cells to provide the positive gate-to-channel voltage comprises applying a program voltage to the control gates of the memory cells;
in response to completion of the programming operation, performing a data retention operation which configures the memory cells to provide a negative gate-to-channel voltage for the memory cells;
wherein:
the memory cells are in NAND strings;
the NAND strings comprise drain-side select gate transistors;
and
the configuring the memory cells to provide the negative gate-to-channel voltage comprises applying a drain voltage to drains of the drain-side select gate transistors and a control gate voltage to control gates of the drain-side select gate transistors which cause the drain-side select gate transistors to charge up the channels by gate-induced drain leakage;
and
performing an erase operation for the set of memory cells, the performing the erase operation comprises applying a drain voltage to the drains of the drain-side select gate transistors and a control gate voltage to the control gates of the drain-side select gate transistors which cause the drain-side select gate transistors to charge up the channels by gate-induced drain leakage, wherein the drain voltage applied to the drains of the drain-side select gate transistors in the data retention operation is lower than the drain voltage applied to the drains of the drain-side select gate transistors in the erase operation.

6 more elements

A memory device, comprising:

a set of memory cells, each memory cell of the set of memory cells comprises a charge-trapping layer;
a set of word lines, the memory cells are connected to different word lines of the set of word lines;
and
a control circuit, the control circuit configured to:
perform an erase operation for the set of memory cells using an erase voltage, the erase operation provides a negative gate-to-channel voltage for the memory cells,
after the erase operation, perform a programming operation for the set of memory cells using a program voltage, the programming operation provides a positive gate-to-channel voltage for the memory cells, and
after the programming operation, perform a data retention operation using a weak erase voltage, weaker than the erase voltage of the erase operation, the data retention operation provide a negative gate-to-channel voltage for the memory cells which is configured to increase a data retention of the memory cells, wherein:
the control circuit, to provide the negative gate-to-channel voltage during the erase operation, is configured to ground control gate voltages for the memory cells while boosting channels of the memory cells;
the control circuit, to provide the negative gate-to-channel voltage during the data retention operation, is configured to ground the control gate voltages for the memory cells while boosting channels of the memory cells;
and
the channels are boosted to a higher level during the erase operation than during the data retention operation.

8 more elements

A memory device, comprising:

a set of memory cells, each memory cell of the set of memory cells comprises a charge-trapping layer;
a set of word lines, the memory cells are connected to different word lines of the set of word lines;
means for performing an erase operation for the set of memory cells using an erase voltage, the means for performing the erase operation comprises means for providing a negative gate-to-channel voltage for the memory cells and grounding control gate voltages for the memory cells while boosting channels of the memory cells;
means for, after the erase operation, performing a programming operation for the set of memory cells using a program voltage, the means for performing the programming operation comprises means for providing a positive gate-to-channel voltage for the memory cells;
and
means for, after the programming operation, performing a data retention operation using a weak erase voltage, weaker than the erase voltage of the erase operation, the means for performing the data retention operation comprises means for providing a negative gate-to-channel voltage for the memory cells and for grounding the control gate voltages for the memory cells while boosting channels of the memory cells, wherein the channels are boosted to a higher level during the erase operation than during the data retention operation.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/518,340Filed 20 Oct 2014
Published: 21 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 16/14
Programming or data input circuits: circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 11/5671
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge trapping in…
G11C 16/0466
Using variable threshold transistors, e.g. FAMOS: comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series