Biasing of unselected blocks of non-volatile memory to reduce loading

A monolithic three-dimensional semiconductor memory device comprising:

• an array of non-volatile memory cells having a plurality of blocks, each formed of a plurality of NAND strings having multiple memory cells connected in series and connected along word lines, where each of a block's NAND strings are connected to a local source line interconnect among a plurality of source lines interconnects,
• wherein the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium, the NAND strings and the local source line interconnects run in a vertical direction relative to the substrate, the word lines run in a horizontal direction relative to the substrate, and each of the local source line interconnects are connected to one of a plurality of global source lines running in the horizontal direction relative to the substrate;
• decoding circuitry connected to the array to select blocks for a memory operation, where the decoding circuitry selects blocks in multi-block groups, the blocks of a group sharing the same global source line among the plurality of global source lines;
• and
• driver circuitry connected to the array, wherein, when performing the memory operation, the driver circuitry applies a source line voltage above ground to the shared global source line of a selected group, applies operating voltages to the word lines of a selected block within the selected group, and applies the source line voltage to the word lines of unselected blocks within the selected group.

A method, comprising:

• performing a memory operation in a memory circuit, the memory circuit comprising an array of non-volatile memory cells having a plurality of blocks, each formed of a plurality of NAND strings having multiple memory cells connected in series and connected along word lines, where each of a block's NAND strings are connected to a common source line among a plurality of common source lines through a local source line interconnect, the memory operation including:
• selecting by decoding circuitry connected to the array for the memory operation, where the decoding circuitry selects blocks in multi-block groups, where the blocks of a group share the same common source line among the plurality of common source lines;
• and
• biasing by driver circuitry of a selected groups of block, including:
• applying a source line voltage higher than ground to the shared common source line of the selected group;
• applying operating voltages to the word lines of a selected block within the selected group;
• and
• applying the source line voltage to the word lines of unselected blocks of the selected group.