US 2016/0111160 A1 · APPARATUSES AND METHODS FOR SEGMENTED SGS LINES

Abstract

Apparatuses and methods for segmented SGS lines are described. An example apparatus ma include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memos subblocks.

Claims28

Dependent claims

An apparatus, comprising:

a first plurality of memory subblocks of a memory block;
a second plurality of memory subblocks of the memory block;
a first select gate control line associated with the first plurality of memory subblocks, the first select gate control line coupled to a first plurality of select gate switches of the first plurality of memory subblocks, the first plurality of select gate switches coupled to a source;
a second select gate control line associated with the second plurality of memory subblocks, the second select gate control line coupled to a second plurality of select gate switches of the second plurality of memory subblocks, the second plurality of select gate switches coupled to the source;
and
a plurality of memory access lines, each memory access line of the plurality of memory access lines associated with each memory subblock of the first plurality of memory subblocks and each memory subblock of the second plurality of memory subblocks.

3 more elements

An apparatus, comprising:

a first select gate source control line associated with a first plurality of memory subblocks;
a second select gate source control line associated with a second plurality of memory subblocks;
a memory subblock of the first plurality of memory subblocks including a first plurality of select gate source switches, each select gate source switch of the first plurality of select gate source switches coupled to the first select gate source control line and configured to be enabled responsive to receipt of an asserted select gate control signal;
a memory subblock of the second plurality of memory subblocks including a second plurality of select gate source switches, each select gate source switch of the second plurality of select gate source switches coupled to the second select gate source control line and configured to be enabled responsive to receipt of the asserted select gate source control signal;
and
a control unit coupled to the first and second select gate source control lines and configured to provide the select gate source control signal to each select gate source switch of the first plurality of select gate source switches using the first select gate source control line responsive to a read operation associated with the memory subblock of the first plurality of memory subblocks, and to provide the select gate source control signal to each select gate source switch of the second plurality of select gate source switches using the second select gate source control line responsive to a read operation associated with the memory subblock of the second plurality of memory subblocks.

3 more elements

Dependencies are inferred from the claim text.

Apparatuses and methods for segmented sgs lines

Life of this patent

Apparatuses and methods for segmented sgs lines

Life of this patent

Abstract

Claims28