Loading patent…
AssigneeCypress Semiconductor Corporation
InventorsJoseph S. Tandingan, Jayant Ashokkumar, David Still, Jesse J. Siman
Estimating the term…
A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.
A memory comprising:
The memory of claim 9, wherein the processing element is configured to issue control signals for the STORE operation comprising control signals for normal programming in which the first transistor is ON and the second and third transistors are OFF, and a plurality of program pulses are applied to a gate node of the NVM element to mitigate an impact of Dynamic Write Inhibit (DWI).
A method of operating a non-volatile Static Random Access Memory (nvSRAM) cell including a volatile charge storage circuit and a non-volatile charge storage circuit, the method comprising:
A method of operating a non-volatile Static Random Access Memory (nvSRAM) cell comprising:
Dependencies are inferred from the claim text.