Cell structure of random access memory, random access memory and operation methods

A random access memory, comprising two identical memory cell arrays, a data write circuit and a data read circuit;

• wherein
• array structures of the two identical memory cell arrays are same, and same original stored information is stored in memory cells with a same address in the two identical memory cell arrays;
• the data write circuit is configured to write same data into the memory cells with the same address in the two identical memory cell arrays;
• the data read circuit is configured to select two pieces of stored information from the memory cells with the same address in the two identical memory cell arrays, and to output “0” if the two pieces of stored information are different or output one of the two pieces of stored information if the two pieces of stored information are same.

A random access memory, comprising a plurality of cell structures of the random access memory, wherein the cell structure of a random access memory comprises:

• a first N-type transistor (N1), a first P-type transistor (P1), a second N-type transistor (NG1) and a second P-type transistor (PG1), in which
• a source electrode of the first N-type transistor (N1) is connected to an adjustable low voltage (VSSI), a source electrode of the first P-type transistor (P1) is connected to an adjustable high voltage (VDDI), a drain electrode of the first N-type transistor (N1) is connected to a gate electrode of the first P-type transistor (P1), a gate electrode of the first N-type transistor (N1) is connected to a drain electrode of the first P-type transistor (P1),
• a drain electrode of the second N-type transistor (NG1) is connected to a bit line (BL), a gate electrode of the second N-type transistor (NG1) is connected to a write word line (WWL), a source electrode of the second N-type transistor (NG1) is connected to a first node (Q) between the gate electrode of the first N-type transistor (N1) and the drain electrode of the first P-type transistor (P1),
• a drain electrode of the second P-type transistor (PG1) is connected to a complementary bit line (BLn), a gate electrode of the second P-type transistor (PG1) is connected to a read word line (RWL), a source electrode of the second P-type transistor (PG1) is connected to a second node (Qn) between the drain electrode of the first N-type transistor (N1) and the gate electrode of the first P-type transistor (P1).