Static random access memory and method of controlling the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Yu LIN, Wei-Cheng WU, Kao-Cheng LIN, Yen-Huei CHEN
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Abstract
A static random access memory (SRAM) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory cell array and the second memory cell array, a primary driver circuit connected to the first data line and a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM.
Claims20
A static random access memory (SRAM) comprising:
- a first memory cell array;
- a second memory cell array;
- a first data line connected to the first memory cell array and the second memory cell array;
- a primary driver circuit connected to the first data line;
- a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM.
A semiconductor device comprising:
- a static random access memory (SRAM) comprising:
- a first memory cell array;
- a second memory cell array;
- a first data line connected to the first memory cell array and the second memory cell array;
- a second data line connected to the first memory cell array and the second memory cell array;
- a primary driver circuit connected to the first data line and the second data line;
- and
- a supplementary driver circuit connected to the first data line and the second data line;
- wherein the supplementary driver circuit is configured to pull a voltage level of the first data line or the second data line to a first voltage level during a write operation of the SRAM.
A method of controlling a static random access memory (SRAM), the method comprising:
- receiving a first control signal on a first data line and a second control signal on a second data line, wherein the first data line and the second data line are connected to a memory cell;
- activating a supplemental driver circuit connected to the first data line and the second data line, wherein the activating the supplemental driver circuit comprises receiving a third control signal on a third data line, wherein the third data line is connected to the memory cell;
- and
- selectively adjusting a voltage signal of the first data line or second data line in response to the third control signal.
Dependencies are inferred from the claim text.