Semiconductor storage device

A semiconductor storage device comprising:

• a first power supply line;
• a second power supply line;
• a first bit line;
• a second bit line;
• a first load transistor having a source coupled to the first power supply line, a drain and a gate;
• a second load transistor having a source coupled to the first power supply line, a drain and a gate;
• a first drive transistor having a source coupled to the second power supply line, a drain and a gate;
• a second drive transistor having a source connected to the second power supply line, a drain and a gate;
• a first transfer transistor having one terminal coupled to the drain of the first drive transistor, and another terminal coupled to the first bit line;
• a second transfer transistor having one terminal coupled to the drain of the second drive transistor, and another terminal coupled to the second bit line;
• a first cell node line which is coupled to the drain of the first load transistor, the drain of the first drive transistor, the gate of the second load transistor, the gate of the second drive transistor and the one terminal of the first transfer transistor;
• a second cell node line which is coupled to the drain of the second load transistor, the drain of the second drive transistor, the gate of the first load transistor, the gate of the first drive transistor and the one terminal of the second transfer transistor;
• a first capacitor line coupled to the first cell node line through a via hole, the first capacitor line being located at a position adjacent to the first bit line in the same wiring layer as that of the first bit line and formed with a longitudinal direction of the first capacitor line set in a direction parallel to the first bit line;
• and
• a second capacitor line connected to the second cell node line through a via hole, the second capacitor line being located at a position adjacent to the second bit line in the same wiring layer as that of the second bit line and formed with a longitudinal direction of the second capacitor line set in a direction parallel to the second bit line,
• wherein
• the first cell node line and the first bit line are formed in different wiring layers and have a portion where the first cell node line and the first bit line overlap each other when viewed from above, and
• the second cell node line and the second bit line are formed in different wiring layers and have a portion where the second cell node line and the second bit line overlap each other when viewed from above.

A semiconductor storage device comprising:

• a first power supply line;
• a second power supply line;
• a first bit line;
• a second bit line;
• a first load transistor having a source coupled to the first power supply line, a drain and a gate;
• a second load transistor having a source coupled to the first power supply line, a drain and a gate;
• a first drive transistor having a source coupled to the second power supply line, a drain and a gate;
• a second drive transistor having a source connected to the second power supply line, a drain and a gate;
• a first transfer transistor having one terminal coupled to the drain of the first drive transistor, and another terminal coupled to the first bit line;
• a second transfer transistor having one terminal coupled to the drain of the second drive transistor, and another terminal coupled to the second bit line;
• a first cell node line which is coupled to the drain of the first load transistor, the drain of the first drive transistor, the gate of the second load transistor, the gate of the second drive transistor and the one terminal of the first transfer transistor;
• a second cell node line which is coupled to the drain of the second load transistor, the drain of the second drive transistor, the gate of the first load transistor, the gate of the first drive transistor and the one terminal of the second transfer transistor;
• wherein
• the first cell node line and the first bit line are formed in different wiring layers and have a first wide portion at a portion where the first cell node line and the first bit line overlap each other when viewed from above,
• the second cell node line and the second bit line are formed in different wiring layers and have a second wide portion at a portion where the second cell node line and the second bit line overlap each other when viewed from above,
• the first wide portion is formed at the first cell node line below the first bit line so as to extend in a direction in which the first bit line extends, and
• the second wide portion is formed at the second cell node line below the second bit line so as to extend in a direction in which the second bit line extends.