Dynamic selection of output delay in a memory control device

A method of operating a memory control device, comprising:

• providing an output signal comprising a data signal or a data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks;
• applying an output delay to a bitstream to be transmitted to generate the output signal, the output delay comprising an aggregate of a de-skew delay and a write-levelization delay;
• and
• adjusting the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks while the de-skew delay remains the same across the plurality of ranks for each of the plurality of write transactions.

A system, comprising:

• a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks;
• and
• a memory control device, coupled to the SDRAM system through a bus, the memory control device comprising:
• an output circuit coupled to provide an output signal comprising a data signal or data strobe signal;
• an output delay unit coupled to apply an output delay to a bitstream to be transmitted to generate the output signal, the output delay comprising an aggregate of a de-skew delay and a write-levelization delay;
• and
• a write-levelization delay controller coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks;
• wherein the de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.