US 2016/0111138 A1Published application

Semiconductor memory device

AssigneeRohm Co., Ltd.

InventorsShintaro IZUMI, Tomoki NAKAGAWA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO

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Abstract

Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.

Claims20

Dependent claims

A semiconductor memory device comprising:

a plurality of memory cells;
a word line commonly connected to the plurality of memory cells;
a plurality of bit lines and a plurality of inverted bit lines respectively connected to the plurality of memory cells;
and
a memory controller operable to control access to the plurality of memory cells,
wherein the plurality of memory cells each include:
an inverter loop connected between a first node and a second node;
a first access transistor connected between the first node and a bit line, the first access transistor being turned on and off according to a voltage applied to the word line;
a second access transistor connected between the second node and an inverted bit line, the second access transistor being turned on and off according to a voltage applied to the word line;
a first node capacitor connected to the first node, the first node capacitor having a higher capacitance than a parasitic capacitor of the bit line;
and
a second node capacitor connected to the second node, the second node capacitor having a higher capacitance than a parasitic capacitor of the inverted bit line, and
wherein, when accessing a memory cell that is a target of a read/write, the memory controller drives the word line to turn on the first and second access transistors without precharging a bit line and an inverted bit line that are connected to a memory cell that is not a target of the read/write.

10 more elements

A plate line driver comprising:

a first output stage operable to generate a second plate line enable signal according to a first plate line enable signal;
a second output stage operable to drive a plate line of a memory cell according to the second plate line enable signal;
and
a boost stage operable to augment driving capacity of the second output stage by lowering the second plate line enable signal to a negative voltage by driving a ferroelectric capacitor according to a boost enable signal.

1 more element

Dependencies are inferred from the claim text.