Address decoding circuit and semiconductor apparatus including the same

An address decoding circuit comprising:

• a main address processing block configured to delay a main address, and output a delayed main address as a second main address;
• a repair block configured to determine whether the main address corresponds to a failed region, and output a repair address according to a determination result;
• a synchronization block configured to synchronize the second main address and the repair address with a synchronization signal, and output a synchronized second main address and a synchronized repair address;
• and
• a decoder configured to decode any one of the synchronized second main address and the synchronized repair address.

A semiconductor apparatus comprising:

• a memory region including a main region and a redundancy region;
• and
• an address decoding circuit configured to process a main address corresponding to the main region,
• the address decoding circuit comprising:
• a main address processing block configured to latch the main address, and output a latched main address;
• a repair block configured to output a repair address and a repair signal, by referring to the main address and information on a failed region;
• a synchronization block configured to synchronize the latched main address, the repair address and the repair signal with a synchronization signal, and output a synchronized main address, a synchronized repair address and a synchronized repair signal;
• and
• a decoder configured to decode any one of the synchronized main address and the synchronized repair address in response to a decoding signal.