Low power high frequency digital pulse frequency modulator

A voltage regulator (VR) comprising:

• mutually coupled on-die inductors for coupling to a load;
• a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch;
• a pulse-width modulator (PWM) controller for controlling the low-side and high-side switches during a first load current;
• and
• a pulse-frequency modulator (PFM) controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising:
• a comparator for comparing output voltage of the load with a reference voltage;
• and
• a first programmable delay line (PDL) coupled to the comparator for determining turn-on duration of the high-side switch.

A system comprising:

• a memory;
• a processor coupled to the memory, the processor including an apparatus which comprises:
• a programmable delay line (PDL) to receive a pulse-width modulated (PWM) signal as input and to generate a first output;
• a selection unit operable to provide PWM signal or its inverted version as a second output;
• and
• a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulated (PFM) output;
• and
• a wireless interface for allowing the processor to communicate with other devices.