Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising:

• maintaining multiple synaptic weights for multiple neurons in a transposable memory array, wherein each synaptic weight of the multiple synaptic weights corresponds to a neuron of the multiple neurons;
• for at least one synaptic weight of the multiple synaptic weights, updating the synaptic weight based on at least one of a learning rule and neuronal firing activity of a corresponding neuron;
• and
• controlling transposable access to the memory array for enhanced learning operation.

A computer program product comprising a computer-readable hardware storage medium having program code embodied therewith, the program code being executable by a computer to implement a method comprising:

• maintaining multiple synaptic weights for multiple neurons in a transposable memory array, wherein each synaptic weight of the multiple synaptic weights corresponds to a neuron of the multiple neurons;
• for at least one synaptic weight of the multiple synaptic weights, updating the synaptic weight based on at least one of a learning rule and neuronal firing activity of a corresponding neuron;
• and
• controlling transposable access to the memory array for enhanced learning operation.