Error Resilient Digital Signal Processing Device
AssigneesImec Vzw, Katholieke Universiteit Leuven, KU LEUVEN R&D
InventorsYanxiang Huang, Chunshu Li, Meng Li
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Abstract
The present disclosure relates to an error resilient scheme for a signal processing device configured to perform iterative processing on clocked input data and to provide output data. The signal processing device includes a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to provide or generate processed data, and a selection circuit configured to provide as the output signal either the processed data or the clocked input data, depending on a control signal representative of a set-up timing error detected in an input data.
Claims15
A signal processing device configured to perform iterative processing on clocked input data and to provide output data, the signal processing device comprising:
- a computation circuit comprising at least one computation unit circuit configured to perform one computation in each iteration on the clocked input data and to generate processed data;
- and
- a selection circuit configured to provide as the output signal either the processed data or the clocked input data depending on a control signal representative of a set-up timing error detected in the input data.
A method for a signal processing device configured to perform iterative processing on clocked input data and to provide output data, wherein the method comprises:
- performing at least one computation on a clocked version of the input data and providing processed data, and
- selecting as an output data either the processed data or the clocked input data depending on a control signal representative of a set-up timing error detected in the input data.
Dependencies are inferred from the claim text.