Simplifying Modes of an Electronic Circuit by Reducing Constraints

A non-transitory computer-readable storage medium storing instructions for simplifying a mode of a circuit design, the instructions for:

• receiving description of a mode of a circuit, the description comprising a netlist and timing constraints associated with the netlist, the netlist comprising timing nodes connected by timing paths and the timing constraints comprising one or more clocks and corresponding exceptions associated with one or more timing paths;
• identifying a set of timing nodes of the circuit, each timing node in the set associated with timing paths reaching the timing node;
• selecting critical clock pairs and corresponding timing exceptions, the selecting comprising, for each timing node in the identified set of timing nodes:
• determining a set of clock pairs and corresponding timing exceptions, each clock pair and corresponding exceptions associated with a timing path reaching the timing node, each clock pair and corresponding exceptions including a launch clock and a capture clock associated with a timing path;
• for each clock pair and corresponding exceptions from the set of clock pairs and corresponding timing exceptions, determining a time interval between an edge of the launch clock and a matching edge of the capture clock;
• identifying a clock pair and corresponding exceptions with a time interval smaller than time intervals of remaining clock pairs in the set;
• and
• marking the identified clock pair as a critical clock pair;
• modifying the description of the mode by eliminating one or more clocks that do not occur in the critical clock pairs;
• and
• performing timing analysis of the circuit using the modified description of the mode.

A computer-implemented system for simplifying a mode of a circuit design, the system comprising:

• a computer processor;
• and
• a computer-readable storage medium storing instruction for executing on the computer processor, the instructions for:
• receiving description of a mode of a circuit, the description comprising a netlist and timing constraints associated with the netlist, the netlist comprising timing nodes connected by timing paths and the timing constraints comprising one or more clocks and corresponding exceptions associated with one or more timing paths;
• identifying a set of timing nodes of the circuit, each timing node in the set associated with timing paths reaching the timing node;
• selecting critical clock pairs and corresponding timing exceptions, the selecting comprising, for each timing node in the identified set of timing nodes:
• determining a set of clock pairs and corresponding timing exceptions, each clock pair and corresponding exceptions associated with a timing path reaching the timing node, each clock pair and corresponding exceptions including a launch clock and a capture clock associated with a timing path;
• for each clock pair and corresponding exceptions from the set of clock pairs and corresponding timing exceptions, determining a time interval between an edge of the launch clock and a matching edge of the capture clock;
• identifying a clock pair and corresponding exceptions with a time interval smaller than time intervals of remaining clock pairs in the set;
• and
• marking the identified clock pair as a critical clock pair;
• modifying the description of the mode by eliminating one or more clocks that do not occur in the critical clock pairs;
• and
• performing timing analysis of the circuit using the modified description of the mode.