Memory protection key architecture with independent user and supervisor domains

A system-on-a chip (SoC) comprising:

• a memory;
• and
• a processor, communicatively coupled to the memory, comprising:
• a processing core to execute a task;
• and
• a memory management unit, coupled to the processing core, comprising:
• a storage unit to store a page table entry comprising one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode;
• a first permission register comprising a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode;
• and
• a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.

A method, comprising:

• determining, by a processing core, an access mode of a task based on a privilege level of the task, wherein the access mode is one of a user-mode access or a supervisor-mode access;
• determining an identifier of a memory frame allocated by the task;
• selecting, by the processing core executing an operating system, a protection key for the task;
• and
• storing the protection key, the access mode, and the identifier in a page table entry of a memory management unit coupled to the processing core.