Data writing method and memory system

A memory data writing method applied to a computer system comprising a CPU, a memory controller and a memory device, wherein the CPU comprises a last level cache (LLC), the method comprising:

• receiving, by the memory controller, update information of a first cache line in the last level cache and data of the first cache line sent by the CPU, wherein the update information of the first cache line indicates an updating status for each of k data blocks in the first cache line, wherein each of the k data blocks has a size equal to a multiple of a burst write size which is a size of a data block that equal to a memory data bus width, k is an integer and 2≦k≦burst length (BL), BL being a number of burst writes required by the memory controller to write data of one cache line into the memory device;
• selecting, by the memory controller, changed data blocks in the first cache line according to the update information of the first cache line in the last level cache;
• generating, by the memory controller, memory addresses of the changed data blocks of the first cache line in the last level cache, wherein each memory address comprises a row address and a column address of one changed data block;
• and
• sending, by the memory controller, the memory addresses corresponding to the changed data blocks and data corresponding to the changed data blocks of the first cache line to the memory device for storing.

A computer system, which comprises a CPU and a memory system, wherein the CPU comprises a last level cache (LLC), and the memory system comprises a memory controller and a memory device, wherein:

• the cache is configured to:
• divide a first cache line of the last level cache into k data blocks according to a burst write size, each of the k data blocks having a size equal to a multiple of the burst write size, wherein the burst write size is determined by a data bus width of the memory device, k is an integer, and 2≦k≦burst length (BL), BL being a number of burst writes required for the memory controller to write data of one cache line of the last level cache into the memory device;
• determine update information of the first cache line, wherein the update information of the first cache line indicates an updating status for each of the k data blocks in the first cache line, and send the update information of the first cache line to the memory controller;
• the memory controller is configured to:
• receive update information of the first cache line in the last level cache and data of the first cache line sent by the CPU, wherein the update information of the first cache line indicates an updating status for each of k data blocks in the first cache line, wherein each of the k data blocks has a size that equal to a multiple of a burst write size which is a size of a data block that equal to a memory data bus width, k is an integer, and 2≦k≦burst length (BL), BL being a number of burst writes required by the memory controller to write data of one cache line into the memory device;
• select changed data blocks in the first cache line according to the update information of the first cache line;
• generate memory addresses of the changed data blocks of the first cache line in the last level cache, wherein each memory address comprises a row address and a column address of one changed data block;
• and send the memory addresses corresponding to the changed data blocks and data corresponding to the changed data blocks of the first cache line to the memory device for storing;
• and
• the memory is configured to:
• receive the memory addresses corresponding to the changed data blocks and data corresponding to the changed data blocks of the first cache line, and perform writing, according to the memory addresses corresponding to the changed data blocks and the data corresponding to the changed data blocks, the data of the changed data blocks in the memory device.