US 2016/0110202 A1 · BRANCH PREDICTION SUPPRESSION

Abstract

A data processing apparatus 2 contains branch prediction circuitry 10 including a micro branch target buffer 28, a full branch target buffer 30 and a global history buffer 32. The branch target buffer entries 40 contain history data 42, 44 which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data 42, 44 indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry 28, 30, 32 is suppressed for these following blocks of program instructions so as to save energy.

Claims16

Dependent claims

Apparatus comprising:

one or more branch prediction circuits to predict whether a given block of program instructions contains a branch instruction;
and
prediction suppression circuitry to use history data representing previous branch behaviour of a following block of program instructions sequentially following said given block of program instructions to suppress at least one of said one or more branch prediction circuits predicting whether said following block of program instructions contains a branch instruction.

Dependencies are inferred from the claim text.

Branch prediction suppression

Life of this patent

Branch prediction suppression

Life of this patent

Abstract

Claims16