Flexible instruction execution in a processor pipeline
AssigneeCavium, Inc.
InventorDavid Albert Carlson
Life of this patent
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Abstract
Executing instructions in a processor includes: selecting or more instructions to be issued together in the same clock cycle of the processor from among a plurality of instructions, the selected one or more instructions occurring consecutively according to a program order; and executing instructions that have been issued, through multiple execution stages of a pipeline of the processor. The executing includes: determining a delay assigned to a first instruction, and sending a result of a first operation performed by the first instruction in a first execution stage to a second execution stage, where the number of execution stages between the first execution stage and the second execution stage is based on the determined delay.
Claims20
A method for executing instructions in a processor, the method comprising:
- selecting or more instructions to be issued together in the same clock cycle of the processor from among a plurality of instructions, the selected one or more instructions occurring consecutively according to a program order;
- and
- executing instructions that have been issued, through multiple execution stages of a pipeline of the processor, the executing including:
- determining a delay assigned to a first instruction, and
- sending a result of a first operation performed by the first instruction in a first execution stage to a second execution stage, where the number of execution stages between the first execution stage and the second execution stage is based on the determined delay.
A processor comprising:
- circuitry configured to select or more instructions to be issued together in the same clock cycle of the processor from among a plurality of instructions, the selected one or more instructions occurring consecutively according to a program order;
- and
- circuitry configured to execute instructions that have been issued, through multiple execution stages of a pipeline of the processor, the executing including:
- determining a delay assigned to a first instruction, and
- sending a result of a first operation performed by the first instruction in a first execution stage to a second execution stage, where the number of execution stages between the first execution stage and the second execution stage is based on the determined delay.
Dependencies are inferred from the claim text.