Flexible instruction execution in a processor pipeline

A processor comprising:

• at least one stage of a pipeline of the processor including circuitry configured to analyze operations to be performed by instructions, the analyzing including:
• determining a latency associated with a first operation to be performed by a first instruction,
• determining a second operation to be performed by a second instruction, where a result of the second operation depends on a result of the first operation, and
• assigning a value to the second instruction corresponding to the determined latency associated with the first operation;
• circuitry configured to select one or more instructions to be issued together in the same clock cycle of the processor from among a plurality of instructions whose operations have been analyzed, the selected one or more instructions occurring consecutively according to a program order;
• and
• circuitry configured to execute instructions that have been issued, through multiple execution stages of the pipeline, and delay a start of execution of the second instruction by a particular number of clock cycles after the clock cycle in which the second instruction is issued according to the value assigned to the second instruction.