Profiling and optimization of program code/application
AssigneeCognitive Electronics, Inc.
InventorAndrew C. Felch
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Abstract
A system and associated methods are disclosed for profiling the execution of program code by a processor. The processor provides an instruction set with special profiling instructions for efficiently determining the bounds and latency of memory operations for blocks of program code. Information gathered regarding the bounds and latency of memory operations are used to determine code optimizations, such as allocation of memory for data structures in memory more local to the processor.
Claims20
A processor comprising:
- circuitry for implementing an instruction set of the processor;
- and circuitry for implementing a register file;
- wherein the register file provides operand inputs for instructions of the instruction set;
- and wherein the instruction set comprises a profiling instruction that receives a first input and a second input from the register file and a third input either from the register file or from a special register whose value was set by a previous instruction.
A method of profiling a block of program code comprising, for each execution of a user memory operation in each of a plurality of executions of the block of program code:
- determining a memory address associated with execution of the user memory operation;
- comparing the determined memory address with a minimum address or a maximum address associated with the block of program code;
- responsive to a determination that the determined memory address is below the minimum address associated with the block of program code or above the maximum address associated with the block of program code, updating the minimum address or maximum address, respectively;
- adding a latency value for the user memory operation to a sum of latency values associated with the block of program code;
- and after all executions of the plurality of executions of the block of program code, comparing a metric derived from the sum of latency values associated with the block of program code to a threshold;
- and responsive at least to the metric derived from the sum of latency values associated with the block of program code exceeding the threshold, generating a proposed optimization of the block of program code.
Dependencies are inferred from the claim text.