All-flash-array primary storage and caching appliances implementing triple-level cell (tlc)-nand semiconductor microchps

A method for storing and caching data in an all-flash-array, comprising:

• erasing, with a processor, a TLC-NAND flash cell;
• programming a first cell voltage level of the TLC-NAND flash cell corresponding to a first binary value, wherein the first binary value equals a first logical value when the first cell voltage level is within a first probability distribution function having a first orientation with respect to a first threshold voltage or a second logical value when the first cell voltage level is within a second probability distribution function having a second orientation with respect to the first threshold voltage;
• and
• storing a first stage value associated with a number of times the TLC-NAND flash cell has been programmed since the TLC-NAND flash cell last was erased.

An apparatus for storing and caching data in an all-flash-array, comprising:

• an array of flash memory modules comprising a plurality of triple-level cell (TLC)-NAND devices;
• a memory array controller coupled to the array of flash memory modules to manage data transfer to and from the array of flash memory modules;
• and
• a remote direct memory access manager to manage data transfer to and from the apparatus;
• wherein at any time no more than a predetermined percent of the TLC-NAND devices are dedicated to a cache region and at least a portion of a remaining TLC-NAND device is dedicated to non-cache primary storage, the TLC-NAND devices dedicated to the cache region are programmed with binary values multiple times in sequence corresponding to multiple sequential stages between erasures, and the binary values are processed in relation to a respective threshold voltage at the multiple sequential stages.

A method for storing and caching data in an all-flash-array, comprising

• erasing, with a processor, a quad-level cell (QLC)-NAND flash cell;
• programming the QLC-NAND flash cell with a respective binary value up to fifteen times in sequence corresponding to up to fifteen sequential stages between erasures;
• interpreting the binary value in relation to one of fifteen threshold voltages at the fifteen sequential stages;
• storing first metadata corresponding to a current stage of the fifteen sequential stages associated with a number of times the QLC-NAND flash cell has been programmed since being erased.