Integrated circuit and low power method of operation
OwnerYedong He, Zhihong Wanginventors
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Abstract
A system-on-chip device operates in a low power mode and keeps on-board peripherals such as FIFO registers operational by maintaining a low frequency bit clock and gating other clock sources. When a peripheral device initiates a DMA (direct memory access) operation, the SOC's bus clock is enabled in response to a signal generated by the peripheral. Once data has been moved between the peripheral and system memory, the bus clock can be gated again.
Claims9
A method of operating an integrated circuit device, the method comprising:
- exchanging data between a peripheral device internal to the integrated circuit and a remote device external to the integrated circuit under the control of a bit rate clock signal;
- disabling a bus clock signal in a first mode of operation;
- and
- enabling the bus clock signal and exchanging data between the peripheral device and system memory under the control of the bus clock signal in a second mode of operation.
Control circuitry for an integrated circuit device, the control circuitry comprising:
- a peripheral device arranged to exchange data with an external device under the control of a received bit rate clock signal in a first mode of operation, and to exchange data with a system memory under the control of a received bus clock signal in a second mode of operation;
- and
- a clock gating module for disabling the bus clock signal in the first mode of operation, and enabling the bus clock signal in the second mode of operation in response to a control signal generated by the peripheral device.
An integrated circuit device capable of operating in a low power mode, the integrated circuit device comprising:
- a system clock generator for generating at least one system clock signal;
- a clock gating module for enabling and disabling the at least one system clock signal, wherein the at least one system clock signal is disabled in the low power mode;
- and
- a peripheral device, wherein in the low power mode, the peripheral device generates control signals that are provided to the clock gating module for enabling a system clock signal that is required by the peripheral device for performing a task, and for disabling the system clock signal after completing the task.
Dependencies are inferred from the claim text.