An apparatus to reduce idle link power in a platform

A system on a chip (SoC) comprising:

• one or more processing cores;
• and
• a root complex coupled to the one or more processing cores to generate transaction requests on behalf of the one or more processor cores, the transaction requests to be communicated between a root port of the root complex and a device, the root port comprising electrical idle (EI) exit detect circuitry and a reference clock source, the root port having a first link state, in which the reference clock source and the EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled and the common mode voltage is not maintained;
• wherein the root port is to transition to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement of the device being greater than or equal to the threshold.