Novel low cost, low power high performance smp/asmp multiple-processor system

An apparatus, comprising:

• a plurality of processors configured to perform multiprocessing functions, the plurality of processors comprising a plurality of first processors and a second processor;
• a controller configured to control operation of the second processor in a first mode and a second mode;
• a clock generation circuit coupled to the controller and configured to generate and output a first clock signal and a second clock signal;
• a switching circuit disposed between the clock generation circuit and the second processor and configured to receive the first and second clock signals and select one for output to the second processor, wherein during the first mode of operation the first clock signal is output to the second processor and during the second mode of operation the second clock signal is output to the second processor;
• wherein during the first mode of operation and the second mode of operation the first clock signal is input to each of the plurality of first processors;
• cache memory coupled to and configured for use with the plurality of processors;
• and
• a clock-domain crossing (CDC) and bypass circuit responsive to the controller and coupled to the second processor and the cache memory, and further configured to provide a clock-domain crossing function between the second processor and the cache memory during the second mode of operation and provide a bypassing function during the first mode of operation.

A method of switching a plurality of processors between a symmetric multiprocessing (SMP) mode and an asymmetric multiprocessing (ASMP) mode, the method comprising:

• operating a first processor in accordance with a first clock signal having a first predetermined frequency and a first supply voltage having a first predetermined operating voltage at all times while the first processor is operating;
• receiving a mode selection signal;
• operating a second processor in a first mode of operation or a second mode of operation in response to the mode selection signal, comprising,
• in the first mode of operation, operating the second processor in accordance with the first clock signal and the first supply voltage, and
• in the second mode of operation, operating the second processor in accordance with a second clock signal having a second predetermined frequency different from the first predetermined frequency and in accordance with a second supply voltage having a second predetermined operating voltage different from the first predetermined operating voltage.

A method for operating a processing system having a plurality of processors in a multiprocessing mode in which at least two processors operate in a symmetric multiprocessing (SMP) mode or an asymmetric multiprocessing (ASMP) mode, the method comprising:

• operating the at least two processors in the SMP mode, wherein the at least two processors receive an SMP clock signal having a first predetermined frequency and receive an SMP operating supply voltage having a first voltage, the at least two processor comprising a first processor and a second processor;
• receiving an instruction to switch from SMP mode to ASMP mode;
• and
• switching operation of the at least two processors from SMP mode to ASMP mode, the switching operation comprising,
• generating an ASMP clock signal having a second predetermined frequency different from the first predetermined frequency,
• generating an ASMP operating supply voltage at a second voltage different from the first voltage,
• inputting the ASMP clock signal and the ASMP operating supply voltage to the second processor, and
• thereafter operating the second processor at the second predetermined frequency and the second voltage and operating the first processor at the first predetermined frequency and the first voltage.

A multi-processor (MP) processing system, comprising:

• a plurality of processors comprising,
• a first processor and a second processor each configured to receive and operate in accordance with a first clock signal having a first predetermined frequency and a first supply voltage having a first predetermined operating voltage,
• a third processor configured to receive and operate in accordance with either the first clock signal or a second clock signal having a second predetermined frequency different from the first predetermined frequency and receive and operate in accordance with a second supply voltage having a second predetermined operating voltage different from the first predetermined operating voltage, and
• a fourth processor configured to receive and operate in accordance with either the first clock signal or a third clock signal having a third predetermined frequency different from the first predetermined frequency and receive and operate in accordance with a third supply voltage having a third predetermined operating voltage different from the first predetermined operating voltage;
• a controller coupled to at least the third and fourth processors and configured to switch operation of the third and fourth processors between a first mode of operation and a second mode of operation, wherein:
• when in the first mode of operation, the third processor and the fourth processor each receives and operates in accordance with the first clock signal and the first supply voltage, and
• when in the second mode of operation, the third processor receives and operates in accordance with the second clock signal and the second supply voltage and the fourth processor receives and operates in accordance with the third clock signal and the third supply voltage;
• and
• wherein the first processor and the second processor are further configured to only receive and operate in accordance with the first clock signal and the first supply voltage during both the first mode and second mode of operation.

A method of switching a plurality of processors between a symmetric multiprocessing (SMP) mode and an asymmetric multiprocessing (ASMP) mode, the method comprising:

• operating a first processor and a second processor in accordance with a first clock signal having a first predetermined frequency and a first supply voltage having a first predetermined operating voltage at all times during operation of the first processor and the second processor;
• receiving a mode selection signal;
• operating a third processor and a fourth processor both in a first mode of operation or a second mode of operation in response to the mode selection signal, comprising,
• in the first mode of operation, operating the third processor and the fourth processor in accordance with the first clock signal and the first supply voltage, and
• in the second mode of operation, operating the third processor in accordance with a second clock signal having a second predetermined frequency different from the first predetermined frequency and in accordance with a second supply voltage having a second predetermined operating voltage different from the first predetermined operating voltage, and operating the fourth processor in accordance with a third clock signal having a third predetermined frequency different from the first predetermined frequency and in accordance with a third supply voltage having a third predetermined operating voltage different from the first predetermined operating voltage.

A method of processing in a multiprocessor system having a plurality of processors, the method comprising:

• processing within the multiprocessor system using only a first active processor within the plurality of processors;
• determining a second processor should be activated for processing within the multiprocessor system;
• in response to the determination, activating the second processor;
• processing within the multiprocessor system using the first active processor and the second active processor in accordance with either a symmetric multiprocessing (SMP) mode or an asymmetric multiprocessing (ASMP) mode, wherein:
• when in the SMP mode, the first active processor and the second active processor each operate in accordance with a first clock signal having a first predetermined frequency and a first supply voltage having a first predetermined voltage, and
• when in the ASMP mode, the first active processor operates in accordance with the first clock signal and the first supply voltage and the second processor operates in accordance with a second clock signal having a second predetermined frequency different from the first predetermined frequency and in accordance with a second supply voltage having a second predetermined operating voltage different from the first predetermined operating voltage;
• receiving a mode selection signal;
• and
• switching operation of the first active processor and the second active processor from either the SMP mode to the ASMP mode or the ASMP mode to the SMP mode depending on the mode selection signal.

A multi-processor (MP) processing system, comprising:

• a plurality of processors comprising,
• a first processor, and
• a second processor;
• a controller coupled to at least the second processor and configured to:
• activate or deactivate the second processor in response to an activation/deactivation signal,
• upon activation of the second processor, control processing within the multiprocessor system using the first processor and the second processor in accordance with either a symmetric multiprocessing (SMP) mode or an asymmetric multiprocessing (ASMP) mode, wherein:
• the SMP mode is defined where the first processor and the second processor each operate in accordance with a first clock signal having a first predetermined frequency and a first supply voltage having a first predetermined voltage, and
• the ASMP mode is defined where the first processor operates in accordance with the first clock signal and the first supply voltage and the second processor operates in accordance with a second clock signal having a second predetermined frequency different from the first predetermined frequency and in accordance with a second supply voltage having a second predetermined operating voltage different from the first predetermined operating voltage,
• receive a mode selection signal, and
• switch operation of the first processor and the second processor from either the SMP mode to the ASMP mode or the ASMP mode to the SMP mode depending on the mode selection signal.