Hardware apparatus and method for multiple processors dynamic asymmetric and symmetric mode switching
AssigneeFuturewei Technologies, Inc.
InventorsWei Chen, Tongzeng Yang, Anthony Mazzola
Life of this patent
Estimating the term…
Abstract
A processing system with multiple processors is switchable between two modes of operation dynamically: symmetrical multi-processing (SMP) and asymmetrical multi-processing (ASMP). The system uses certain criteria to determine when to switch to improve the power consumption or performance. A controller enables control and fast-switching between the two modes. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control voltage supplies and CPU/memory clocks to the multiple processors and cache memory.
Claims23
A multi-processing system, comprising:
- a plurality of processors, each processor configured to receive a clock signal having a predetermined frequency and receive a supply voltage having a predetermined operating voltage;
- and
- a controller coupled to the plurality of processors and configured to switch operation of the plurality of processors between a first mode of operation and a second mode of operation, wherein:
- when in the first mode of operation, the plurality of processors perform symmetric multi-processing (SMP) and,
- when in the second mode of operation, the plurality of processors perform asymmetric multi-processing (ASMP).
An apparatus, comprising:
- a plurality of processors configured to perform multiprocessing functions;
- a controller configured to control operation of the plurality of processors in a first mode and a second mode;
- a clock generation circuit coupled to the controller and configured to generate and output a plurality of clock signals.
- an operating voltage generation circuit coupled to the controller and configured to generate and output a plurality of operating supply voltage signals;
- a switching circuit disposed between the clock generation circuit and the plurality of processors and configured to receive the plurality of clock signals and output a second plurality of clock signals to the plurality of processors, wherein during the first mode of operation, the second plurality of clock signals each have a same predetermined frequency, and during the second mode of operation, the second plurality of clock signals each have a different predetermined frequency;
- cache memory coupled to and configured for use with the plurality of processors;
- and
- a clock-domain crossing (CDC) and bypass circuit responsive to the controller and coupled to the plurality of processors and the cache memory, and further configured to provide a clock-domain crossing function between the plurality of processors and the cache memory during the second mode of operation and provide a bypassing function during the first mode of operation.
A method for switching a processing system having a plurality of processors between a symmetric multiprocessing (SMP) mode and an asymmetric multiprocessing (ASMP) mode, the method comprising:
- receiving an instruction to switch between the SMP mode and the ASMP mode;
- and
- switching the mode of operation of the processing system in accordance with the received instruction, wherein switching the mode of operation comprises,
- when the processing system is currently operating in the SMP mode, generating a plurality of ASMP clock signals each having a different ASMP predetermined frequency, and inputting each of the plurality of ASMP clock signals to a different processor of the plurality of processors for operation of the respective processor at the respective ASMP predetermined frequency, and
- when the processing system is currently operating in the ASMP mode, generating an SMP clock signal having an SMP predetermined frequency, and inputting the SMP clock signal to each processor of the plurality of processors for operation of each processor at the SMP predetermined frequency.
Dependencies are inferred from the claim text.