Thin film transistor substrate and liquid crystal display including the same

A liquid crystal display comprising:

• a first substrate;
• a gate line and a plurality of storage electrode lines formed on the first substrate;
• a gate insulating layer formed on the gate line;
• a semiconductor layer formed on the gate insulating layer;
• a data line, a drain electrode, and a divided reference voltage formed on the semiconductor layer;
• a passivation layer covering the data line, the drain electrode, and the divided reference voltage line, wherein a first contact hole and a second contact hole are formed in the passivation layer partially exposing the drain electrode;
• a first subpixel electrode and a second subpixel electrode electrically connected with the drain electrode through the first and second contact holes, respectively, wherein the first subpixel electrode and the second subpixel electrode include a plurality of vertical stems, a plurality of horizontal stems, and a plurality of branch electrodes, and wherein the first subpixel electrode is formed above the gate line and the second subpixel electrode is formed below the gate line;
• a second substrate disposed corresponding to the first substrate;
• a common electrode formed on the second substrate;
• a liquid crystal layer disposed between the first substrate and the second substrate;
• and
• a first protrusion formed in the plurality of vertical stems of the first subpixel electrodes and the plurality of vertical stems of the second subpixel electrode.

A thin film transistor array panel comprising:

• a first substrate;
• a gate line and a plurality of storage electrodes formed on the first substrate;
• a gate insulating layer formed on the gate line;
• a semiconductor layer formed on the gate insulating layer;
• a data line, a drain electrode, and a divided reference voltage line formed on the semiconductor layer;
• a passivation layer covering the data line, the drain electrode, and the divided reference voltage line, wherein a first contact hole and a second contact hole are formed in the passivation layer partially exposing the drain electrode;
• a first subpixel electrode and a second subpixel electrode electrically connected with the drain electrode through the first and second contact holes, respectively, wherein the first subpixel electrode and the second subpixel electrode include a plurality of vertical stems, a plurality of horizontal stems, and a plurality of branch electrodes;
• and
• a protrusion formed at a portion where the first and second subpixel electrodes overlap the data line, wherein the protrusion protrudes to a same height as the data line.