3d stacked die test architecture

An integrated circuit comprising:

• (a) a test data in lead, a test clock lead, a test mode select lead, a test data out lead, an update lead, and a capture lead;
• (b) a TAP state machine having a clock input coupled to the test clock lead, a mode input coupled to the test mode select lead, data register control outputs, and instruction register control outputs;
• (c) an instruction register having a test data input coupled to the test data in lead, instruction register control inputs coupled to the instruction register control outputs, and instruction register outputs;
• (d) data registers having test data inputs coupled to the test data in lead, data register control inputs, and instruction register control inputs coupled to the instruction register outputs;
• and
• (e) dual port router circuitry having an update input coupled to the update lead, a capture input coupled to the capture lead, data register control inputs coupled to the data register control outputs of the TAP state machine, instruction register inputs coupled to the instruction register outputs, and data register control outputs coupled to the data register control inputs of the data registers.