US 2016/0109514 A1Published application

Structural testing of integrated circuits

AssigneeFreescale Semiconductor, Inc.

InventorsAnurag Jindal, Nipun Mahajan

Life of this patent

Estimating the term…

Loading patent…

Abstract

An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.

Claims15

Dependent claims

An integrated circuit operable in scan test and functional modes when connected to an automated test equipment (ATE) for testing the integrated circuit, the integrated circuit comprising:

a first set of input/output (IO) pads, connected to the ATE for receiving a plurality of test patterns when the integrated circuit is in the scan test mode;
a decompressor, connected to the first set of IO pads, for receiving and decompressing the plurality of test patterns and generating a corresponding plurality of decompressed test patterns when the integrated circuit is in the scan test mode;
a plurality of scan chains, connected to the decompressor, for receiving the plurality of decompressed test patterns and generating a corresponding plurality of test responses when the integrated circuit is in the functional mode;
a compressor, connected to the plurality of scan chains for receiving and compressing the plurality of test responses and generating a plurality of compressed test responses when the integrated circuit is in the scan test mode;
a second set of IO pads, connected to the ATE for receiving a plurality of masking signals when the integrated circuit is in the scan test mode;
and
a scan controller, connected to the compressor, including:
a plurality of logic gates, wherein each logic gate has a first input terminal connected to the compressor for receiving a compressed test response of the plurality of compressed test responses, a second input terminal connected to an IO pad of the second set of IO pads for receiving a masking signal of the plurality of masking signals, and an output terminal for outputting a masked signal based on a logic state of the masking signal when the integrated circuit is in the scan test mode;
and
a multiple input shift register (MISR) having a clock input terminal connected to the ATE, for receiving a tester clock signal, and a plurality of input terminals, wherein each of the plurality of input terminals is connected to a corresponding output terminal of a logic gate of the plurality of logic gates, for receiving masked signals generated by each of the plurality of logic gates and generating a signature such that a non-deterministic value of a compressed test response of the plurality of compressed test responses is masked when the integrated circuit is in the scan test mode.

7 more elements

An integrated circuit operable in scan test and functional modes when connected to an automated test equipment (ATE) for testing the integrated circuit, comprising:

a set of input/output (IC)) pads, connected to the ATE, for receiving a plurality of test patterns and a plurality of masking signals when the integrated circuit is in the scan test mode;
a plurality of flip-flops, wherein each flip-flop of the plurality of flip-flops has a clock input terminal connected to the ATE, for receiving a tester clock signal, an input terminal connected to a corresponding IO pad of the set of IO pads, for receiving a test pattern of the plurality of test patterns, and an output terminal for outputting a synchronized test pattern when the integrated circuit is in the scan test mode;
a decompressor, connected to the output terminals of the plurality of flip-flops, for receiving and decompressing synchronized test patterns generated by each of the plurality of flip-flops and generating a corresponding plurality of decompressed test patterns when the integrated circuit is in the scan test mode;
a plurality of scan chains, connected to the decompressor, for receiving the plurality of decompressed test patterns and generating a corresponding plurality of test responses when the integrated circuit is in the functional mode;
a compressor, connected to the plurality of scan chains for receiving and compressing the plurality of test responses and generating a plurality of compressed test responses when the integrated circuit is in the scan test mode;
and
a scan controller, connected to the compressor, including:
a plurality of logic gates, wherein each logic gate of the plurality of logic gates has a first input terminal connected to the compressor for receiving a compressed test response of the plurality of compressed test responses, a second input terminal connected to an IO pad of the set of IO pads for receiving a masking signal of the plurality of masking signals, and an output terminal for outputting a masked signal based on a logic state of the masking signal when the integrated circuit is in the scan test mode;
and
a multiple input shift register (MISR) having a clock input terminal connected to the ATE for receiving the tester clock signal, a plurality of input terminals connected to corresponding output terminals of the plurality of logic gates for receiving masked signals generated by each of the plurality of logic gates and generating a signature such that a non-deterministic value of a compressed test response of the plurality of compressed test responses is masked when the integrated circuit is in the scan test mode.

7 more elements

Dependencies are inferred from the claim text.