Device testing
AssigneeInfineon Technologies AG
InventorsGiovanni CAPODIVACCA, Adolfo DE CICCO
Life of this patent
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Abstract
A device may include a plurality of cells. Each cell may include a field-effect transistor and a switch configured to selectively connect a second contact of the respective field-effect transistor with a common test line of the device. A controller of the device is configured to control the switch to be in a closed position. At least one pin is provided which is configured to apply a stress voltage to a common power line connected to a first contact with the field-effect transistor and to the common test line.
Claims20
A device, comprising:
- a common power line,
- a common test line, and
- a plurality of cells,
- wherein each one of the plurality of cells comprises:
- a field-effect transistor comprising a gate, a first contact, and a second contact, the first contact being one of a source and a drain of the field-effect transistor and being coupled to the common power line, the second contact being the other one of the source and the drain, and
- a switch configured to selectively couple the second contact of the respective field-effect transistor with the common test line in a closed position,
- wherein the device further comprises:
- a controller configured to control the switches of the plurality of cells to be in the closed position,
- at least one pin configured to apply a stress voltage to the common power line and the common test line when at least one of the switches is in the closed position.
A method of applying a stress voltage to a source and a drain of a plurality of field-effect transistors when executing a gate stress, each one of the plurality of field-effect transistors being associated with one of a plurality of cells of a device, the method comprising:
- for each one of the plurality cells:
- controlling a switch of the respective cell to be in a closed position, said switch coupling one of the source and the drain of the field-effect transistor of the respective cell with a common test line of the device in the closed position, the other one of the source and the drain being coupled to a common power line of the device, and
- via at least one pin, applying the stress voltage to the common power line and to the common test line when at least one of the switches is in the closed position.
A method of applying a stress voltage, comprising:
- controlling a switch of a cell to be in a closed position, the switch coupling one of a source and a drain of a field-effect transistor with a common test line, the switch further coupling one of the source and the drain to a common power line, and
- applying the stress voltage to the common power line and to the common test line when the switch is in the closed position.
Dependencies are inferred from the claim text.