Circuit and method for testing transistor(s)

Abstract

Disclosed is a circuit and method for testing transistor(s). The circuit is used for testing a set of transistors including at least two transistors, wherein the circuit comprises: a first power supply voltage terminal connected to first electrodes of the respective transistors; a first control signal terminal connected to control electrodes of the respective transistors; and a set of test terminals including at least two test terminals, wherein the test terminals are connected to second electrodes of the corresponding transistors, respectively. According to the circuit disclosed in the present disclosure, it can be achieved that the bias voltages can be applied to the plurality of transistors to be tested simultaneously. Further, the current characteristics of the transistors are tested respectively, which avoids applying the bias voltage to the plurality of transistor to be tested one by one, thus reducing the time consumed in test and improving the testing efficiency

Dependencies are inferred from the claim text.