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US 2016/0109503 A1Published application
Jig, manufacturing method thereof and test method
AssigneeKabushiki Kaisha Toshiba
InventorsHirofumi ONO, Hiroaki MURAKAMI
Life of this patent
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Abstract
In accordance with an embodiment, a jig includes a substrate, a plurality of wiring lines on the substrate, and an electrode on one end of each of the wiring lines. The electrode is located so as to correspond to a location of an electrode of an external semiconductor chip and includes gold (Au), silver (Ag), aluminum (Al), tin (Sn), or indium (In).
Claims14
A jig comprising:
- substrate;
- a plurality of wiring lines on the substrate;
- and
- an electrode which is formed by a conductive material on one end of each of the wiring lines and is located so as to correspond to a location of an electrode of an external semiconductor chip,
- wherein the electrode comprises gold (Au), silver (Ag), aluminum (Al), tin (Sn), or indium (In).
2 more elements
A manufacturing method of a jig, the method comprising:
- forming a plurality of wiring lines on the surface of a substrate;
- and
- forming an electrode on one end of each of the wiring lines by using gold (Au), silver (Ag), aluminum (Al), tin (Sn), or indium (In),
- wherein the jig is used in a test of a semiconductor chip.
1 more element
A test method comprising:
- preparing a jig, the jig comprising a first substrate, a plurality of wiring lines on the first substrate, and an electrode formed on one end of each of the wiring lines by using gold (Au), silver (Ag), aluminum (Al), tin (Sn), or indium (In), the electrode being provided to correspond to electrode arrangement of a semiconductor chip which is a test piece;
- aligning so such a manner that an electrode of the semiconductor chip abuts on the electrode of the jig, attaching the test piece to the first substrate by using pressure thereby bringing the electrode of the semiconductor chip into contact with the electrode of the jig;
- and
- applying a test signal to the semiconductor chip via the wiring lines, and detecting and analyzing an output signal from the semiconductor chip or light generated from the test piece.
1 more element
Dependencies are inferred from the claim text.